1. Field of the Invention
The present invention relates generally to a liquid crystal display unit having a plurality of pixels arrayed in a matrix.
2. Description of the Related Art
A single pixel in a liquid crystal display panel is schematically illustrated in FIG. 8, which corresponds generally to Japanese Patent No. 63-41708. In FIG. 8, the pixel, also referred to as a liquid crystal cell LC, includes a transparent pixel electrode 1, the pixel electrode 1 being formed on a transparent substrate which, along with a second transparent substrate, sandwiches a liquid crystal material therebetween. A switching thin-film transistor 2 is provided for driving the pixel electrode 1; an address line 3 is provided for selecting a row of individual pixels and is located between rows of pixel electrodes 1; and a signal line 4 which is disposed between columns of the pixel electrodes 1 supplies an image signal to the electrodes. Each thin film transistor 2 is provided with a drain 2d that is connected to the pixel electrode 1, a source 2s that is connected to the signal line 4, and a gate 2g that is connected to the address line 3.
In FIG. 9 is shown an equivalent circuit for each pixel, or liquid crystal cell, LC. In a liquid crystal display panel, it is necessary to add a storage capacitor Cs for each of the pixels LC to improve image quality. The capacitance value of the storage capacitor Cs is to be maximized to prevent flicker. The storage capacitor Cs may be produced by superimposing the pixel electrode 1 on a portion of the address line 3 or on a portion of the signal line 4 with an interlayer insulator film positioned therebetween. In the example illustrated in FIG. 8, the storage capacitor Cs is formed between the pixel electrode 1 and the address line 3.
At present, technical development in liquid crystal display panels is directed toward achieving a larger image area and a higher resolution. However, as the pixel pitch is decreased for enhanced resolution, it become impossible to obtain a sufficiently large capacitance value of the storage capacitor Cs produced by superimposing the pixel electrode 1 on the address line 3 or on the signal line 4 as described above. To achieve a sufficiently great capacitance value, there may be contrived a means for producing an exclusive electrode wire for the capacitance alone so as to form a storage capacitor Cs of desired value between the pixel electrode and such exclusive wire. Since such exclusive electrode wire can be supplied with a fixed potential, it is not affected in a harmful way by any potential variation in the address line relative to the signal line to eventually obtain enhancement of the image quality. However, to realize such exclusive electrode wire producing means without changing the aperture rate, or aperture ratio, of the pixel, the exclusive electrode wire for the capacitor Cs needs to be composed of a transparent material or the like. This unfortunately increases the number of steps in the manufacturing process and results in disadvantages with respect to yield rate and production cost.
Referring again to FIG. 8, the pixel electrode 1 is provided with a square setback la in a portion where the thin film transistor 2 is formed. The drain 2d of the thin film transistor 2 is connected to the pixel electrode 1 and the source 2s is connected to the signal line 4 in such a way that the thin film transistor 2 bridges the square setback 1a in the pixel electrode 1. The gate 2g of the transistor 2 is connected to a contact portion 3a which extends from the address line 3 toward the square setback 1a.
Generally, in a liquid crystal display unit comprising a plurality of pixels arrayed in a matrix with switching transistors, it is necessary to lower the on-resistance of the switching transistor 2 for supplying a signal to the liquid crystal cell LC during the selection period.
In liquid crystal display units where thin film transistors 2 are composed of amorphous silicon or polycrystaline silicon for use as switching transistors, the mobility of charge carriers is low so that a ratio W/L of channel width W to channel length L (as shown if FIG. 8) is set to a relatively great value to lower the on-resistance of the thin film transistor 2. Accordingly, this enlarges the area of the thin film transistor 2 and results in a decrease in the area of the pixel portion which leads to a decrease in the aperture rate, or aperture ratio, of the pixels. Thus, the attempt to reduce pixel area while enhancing resolution consequently fails.